1. Field
The embodiment relates to circuit design simulation, and especially relates to a method of checking current density limitation and an apparatus for checking current density limitation.
2. Description of the Related Art
During the design of Large Scale Integration (LSI) circuits by conventional simulation, current density limitation is checked using the results of a power consumption calculation and a current density calculation. The conventional current density limitation check is performed after cell placement, wiring on a substrate, and timing convergence on timing verification. The conventional current density limitation check compares the current value of each power supply wiring with the allowable current value of each power supply wiring. The current value flowing into each via connecting between the power supply wirings is compared to the allowable current value of each via. Finally, the current value flowing into each via is judged whether it is within the allowable current values or not.
The conventional LSI design method recognizes vias connecting between powers supply wiring, and power supply wirings that exist in the upper and lower layers for the power supply wiring, as a node. Therefore, the connection relation between the power supply wirings and the vias is not recognized accurately. As a result, the current density limitation check is performed by dividing power supply wirings and vias. An allowable current value on a connected field side with one via of a power supply wiring is set for an allowable current of a power supply wiring. Because the allowable current value of the power supply wiring is larger than the allowable current value on the connected field side, however, the allowable current value on the connected field side is used to judge whether the current value is within the allowable current values or not.
However, the conventional LSI design method underestimates the allowable current value of a power supply wiring, which results in increased Turn Around Time (TAT) and larger chip sizes, due to unnecessary reinforcement of power supply wiring and reallocation of cells.